MPL3115A2_Arduino 1.0.1
This library enables the developer to evaluate NXP MPL3115A2(S) with Arduino.
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mpl3115.h
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1
8#ifndef MPL3115_H_
9#define MPL3115_H_
10
15enum {
16 MPL3115_STATUS = 0x00,
17 MPL3115_OUT_P_MSB = 0x01,
18 MPL3115_OUT_P_CSB = 0x02,
19 MPL3115_OUT_P_LSB = 0x03,
20 MPL3115_OUT_T_MSB = 0x04,
21 MPL3115_OUT_T_LSB = 0x05,
22 MPL3115_DR_STATUS = 0x06,
23 MPL3115_OUT_P_DELTA_MSB = 0x07,
24 MPL3115_OUT_P_DELTA_CSB = 0x08,
25 MPL3115_OUT_P_DELTA_LSB = 0x09,
26 MPL3115_OUT_T_DELTA_MSB = 0x0A,
27 MPL3115_OUT_T_DELTA_LSB = 0x0B,
28 MPL3115_WHO_AM_I = 0x0C,
29 MPL3115_F_STATUS = 0x0D,
30 MPL3115_F_DATA = 0x0E,
31 MPL3115_F_SETUP = 0x0F,
32 MPL3115_TIME_DLY = 0x10,
33 MPL3115_SYSMOD = 0x11,
34 MPL3115_INT_SOURCE = 0x12,
35 MPL3115_PT_DATA_CFG = 0x13,
36 MPL3115_BAR_IN_MSB = 0x14,
37 MPL3115_BAR_IN_LSB = 0x15,
38 MPL3115_P_TGT_MSB = 0x16,
39 MPL3115_P_TGT_LSB = 0x17,
40 MPL3115_T_TGT = 0x18,
41 MPL3115_P_WND_MSB = 0x19,
42 MPL3115_P_WND_LSB = 0x1A,
43 MPL3115_T_WND = 0x1B,
44 MPL3115_P_MIN_MSB = 0x1C,
45 MPL3115_P_MIN_CSB = 0x1D,
46 MPL3115_P_MIN_LSB = 0x1E,
47 MPL3115_T_MIN_MSB = 0x1F,
48 MPL3115_T_MIN_LSB = 0x20,
49 MPL3115_P_MAX_MSB = 0x21,
50 MPL3115_P_MAX_CSB = 0x22,
51 MPL3115_P_MAX_LSB = 0x23,
52 MPL3115_T_MAX_MSB = 0x24,
53 MPL3115_T_MAX_LSB = 0x25,
54 MPL3115_CTRL_REG1 = 0x26,
55 MPL3115_CTRL_REG2 = 0x27,
56 MPL3115_CTRL_REG3 = 0x28,
57 MPL3115_CTRL_REG4 = 0x29,
58 MPL3115_CTRL_REG5 = 0x2A,
59 MPL3115_OFF_P = 0x2B,
60 MPL3115_OFF_T = 0x2C,
61 MPL3115_OFF_H = 0x2D,
62};
63
64#define MPL3115_I2C_ADDRESS (0x60) /*MPL3115A2 Address*/
65#define MPL3115_WHOAMI_VALUE (0xC4)
68/*--------------------------------
69** Register: STATUS
70** Enum: MPL3115_STATUS
71** --
72** Offset : 0x00 - Alias for DR_STATUS or F_STATUS.
73** ------------------------------*/
74typedef uint8_t MPL3115_STATUS_t;
75
76
77
78/*--------------------------------
79** Register: OUT_P_MSB
80** Enum: MPL3115_OUT_P_MSB
81** --
82** Offset : 0x01 - Bits 12-19 of 20-bit real-time Pressure sample.
83** ------------------------------*/
84typedef uint8_t MPL3115_OUT_P_MSB_t;
85
86
87/*--------------------------------
88** Register: OUT_P_CSB
89** Enum: MPL3115_OUT_P_CSB
90** --
91** Offset : 0x02 - Bits 4-11 of 20-bit real-time Pressure sample.
92** ------------------------------*/
93typedef uint8_t MPL3115_OUT_P_CSB_t;
94
95
96/*--------------------------------
97** Register: OUT_P_LSB
98** Enum: MPL3115_OUT_P_LSB
99** --
100** Offset : 0x03 - Bits 0-3 of 20-bit real-time Pressure sample.
101** ------------------------------*/
102typedef union {
103 struct {
104 uint8_t _reserved_ : 4;
105 uint8_t pd : 4; /* - 20-bit pressure sample measurement data bits 3:0 */
106
107 } b;
108 uint8_t w;
109} MPL3115_OUT_P_LSB_t;
110
111
112/*
113** OUT_P_LSB - Bit field mask definitions
114*/
115#define MPL3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0)
116#define MPL3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4)
117
118
119/*------------------------------*/
120
121
122
123/*--------------------------------
124** Register: OUT_T_MSB
125** Enum: MPL3115_OUT_T_MSB
126** --
127** Offset : 0x04 - Bits 4-11 of 12-bit real-time Temperature sample.
128** ------------------------------*/
129typedef uint8_t MPL3115_OUT_T_MSB_t;
130
131
132/*--------------------------------
133** Register: OUT_T_LSB
134** Enum: MPL3115_OUT_T_LSB
135** --
136** Offset : 0x05 - Bits 0-3 of 12-bit real-time Temperature sample.
137** ------------------------------*/
138typedef union {
139 struct {
140 uint8_t _reserved_ : 4;
141 uint8_t pd : 4; /* - 12-bit temperature sample measurement data bits 3:0 */
142
143 } b;
144 uint8_t w;
145} MPL3115_OUT_T_LSB_t;
146
147
148/*
149** OUT_T_LSB - Bit field mask definitions
150*/
151#define MPL3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0)
152#define MPL3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4)
153
154
155/*------------------------------*/
156
157
158
159/*--------------------------------
160** Register: DR_STATUS
161** Enum: MPL3115_DR_STATUS
162** --
163** Offset : 0x06 - Data-ready status information
164** ------------------------------*/
165typedef union {
166 struct {
167 uint8_t _reserved_ : 1;
168 uint8_t tdr : 1; /* Temperature new Data Available. */
169
170 uint8_t pdr : 1; /* Pressure/Altitude new data available. */
171
172 uint8_t ptdr : 1; /* Pressure/Altitude OR Temperature data ready. */
173
174 uint8_t _reserved_1 : 1;
175 uint8_t tow : 1; /* Temperature data overwrite. */
176
177 uint8_t pow : 1; /* Pressure/Altitude data overwrite. */
178
179 uint8_t ptow : 1; /* Pressure/Altitude OR Temperature data overwrite. */
180
181 } b;
182 uint8_t w;
183} MPL3115_DR_STATUS_t;
184
185
186/*
187** DR_STATUS - Bit field mask definitions
188*/
189#define MPL3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02)
190#define MPL3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1)
191
192#define MPL3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04)
193#define MPL3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2)
194
195#define MPL3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08)
196#define MPL3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3)
197
198#define MPL3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20)
199#define MPL3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5)
200
201#define MPL3115_DR_STATUS_POW_MASK ((uint8_t) 0x40)
202#define MPL3115_DR_STATUS_POW_SHIFT ((uint8_t) 6)
203
204#define MPL3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80)
205#define MPL3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7)
206
207
208/*
209** DR_STATUS - Bit field value definitions
210*/
211#define MPL3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition is */
212 /* completed. Cleared anytime OUT_T_MSB register is */
213 /* read, when F_MODE is zero */
214#define MPL3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */
215 /* acquisition is completed. Cleared anytime OUT_P_MSB */
216 /* register is read, when F_MODE is zero */
217#define MPL3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */
218 /* Pressure/Altitude or Temperature is available. */
219 /* Cleared anytime OUT_P_MSB or OUT_T_MSB register is */
220 /* read, when F_MODE is zero */
221#define MPL3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */
222 /* completed before the retrieval of the previous */
223 /* data. When this occurs the previous data is */
224 /* overwritten. Cleared anytime OUT_T_MSB register is */
225 /* read, when F_MODE is zero */
226#define MPL3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */
227 /* acquisition is completed before the retrieval of */
228 /* the previous data. When this occurs the previous */
229 /* data is overwritten. POW is cleared anytime */
230 /* OUT_P_MSB register is read, when F_MODE is zero */
231#define MPL3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */
232 /* completing the retrieval of the previous set. This */
233 /* event occurs when the content of at least one data */
234 /* register (i.e. OUT_P, OUT_T) has been overwritten. */
235 /* PTOW is cleared when the high-bytes of the data */
236 /* (OUT_P_MSB or OUT_T_MSB) are read, when F_MODE is */
237 /* zero */
238/*------------------------------*/
239
240
241
242/*--------------------------------
243** Register: OUT_P_DELTA_MSB
244** Enum: MPL3115_OUT_P_DELTA_MSB
245** --
246** Offset : 0x07 - Bits 12-19 of 20-bit Pressure change data.
247** ------------------------------*/
248typedef uint8_t MPL3115_OUT_P_DELTA_MSB_t;
249
250
251/*--------------------------------
252** Register: OUT_P_DELTA_CSB
253** Enum: MPL3115_OUT_P_DELTA_CSB
254** --
255** Offset : 0x08 - Bits 4-11 of 20-bit Pressure change data.
256** ------------------------------*/
257typedef uint8_t MPL3115_OUT_P_DELTA_CSB_t;
258
259
260/*--------------------------------
261** Register: OUT_P_DELTA_LSB
262** Enum: MPL3115_OUT_P_DELTA_LSB
263** --
264** Offset : 0x09 - Bits 0-3 of 20-bit Pressure change data.
265** ------------------------------*/
266typedef union {
267 struct {
268 uint8_t _reserved_ : 4;
269 uint8_t pcd : 4; /* - 20-bit pressure change measurement data bits 3:0 */
270
271 } b;
272 uint8_t w;
273} MPL3115_OUT_P_DELTA_LSB_t;
274
275
276/*
277** OUT_P_DELTA_LSB - Bit field mask definitions
278*/
279#define MPL3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0)
280#define MPL3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4)
281
282
283/*------------------------------*/
284
285
286
287/*--------------------------------
288** Register: OUT_T_DELTA_MSB
289** Enum: MPL3115_OUT_T_DELTA_MSB
290** --
291** Offset : 0x0A - Bits 4-11 of 12-bit Temperature change data.
292** ------------------------------*/
293typedef uint8_t MPL3115_OUT_T_DELTA_MSB_t;
294
295
296/*--------------------------------
297** Register: OUT_T_DELTA_LSB
298** Enum: MPL3115_OUT_T_DELTA_LSB
299** --
300** Offset : 0x0B - Bits 0-3 of 12-bit Temperature change data.
301** ------------------------------*/
302typedef union {
303 struct {
304 uint8_t _reserved_ : 4;
305 uint8_t tcd : 4; /* - 12-bit temperature change measurement data bits 3:0 */
306
307 } b;
308 uint8_t w;
309} MPL3115_OUT_T_DELTA_LSB_t;
310
311
312/*
313** OUT_T_DELTA_LSB - Bit field mask definitions
314*/
315#define MPL3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0)
316#define MPL3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4)
317
318
319/*------------------------------*/
320
321
322
323/*--------------------------------
324** Register: WHO_AM_I
325** Enum: MPL3115_WHO_AM_I
326** --
327** Offset : 0x0C - Fixed Device ID Number.
328** ------------------------------*/
329typedef uint8_t MPL3115_WHO_AM_I_t;
330
331
332
333/*--------------------------------
334** Register: F_STATUS
335** Enum: MPL3115_F_STATUS
336** --
337** Offset : 0x0D - FIFO Status: No FIFO event detected.
338** ------------------------------*/
339typedef union {
340 struct {
341 uint8_t f_cnt : 6; /* FIFO sample counter. F_CNT[5:0] bits indicate the number of samples */
342 /* currently stored in the FIFO buffer */
343
344 uint8_t f_wmkf_flag : 1; /* FIFO Watermark event */
345
346 uint8_t f_ovf : 1; /* FIFO overflow event. */
347
348 } b;
349 uint8_t w;
350} MPL3115_F_STATUS_t;
351
352
353/*
354** F_STATUS - Bit field mask definitions
355*/
356#define MPL3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
357#define MPL3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
358
359#define MPL3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40)
360#define MPL3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6)
361
362#define MPL3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
363#define MPL3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
364
365
366/*
367** F_STATUS - Bit field value definitions
368*/
369#define MPL3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */
370#define MPL3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */
371#define MPL3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */
372#define MPL3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */
373/*------------------------------*/
374
375
376
377/*--------------------------------
378** Register: F_DATA
379** Enum: MPL3115_F_DATA
380** --
381** Offset : 0x0E - FIFO 8-bit data access.
382** ------------------------------*/
383typedef uint8_t MPL3115_F_DATA_t;
384
385
386
387/*--------------------------------
388** Register: F_SETUP
389** Enum: MPL3115_F_SETUP
390** --
391** Offset : 0x0F - FIFO setup.
392** ------------------------------*/
393typedef union {
394 struct {
395 uint8_t f_wmrk : 6; /* FIFO Event Sample Count Watermark. */
396
397 uint8_t f_mode : 2; /* FIFO buffer overflow mode. */
398
399 } b;
400 uint8_t w;
401} MPL3115_F_SETUP_t;
402
403
404/*
405** F_SETUP - Bit field mask definitions
406*/
407#define MPL3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
408#define MPL3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
409
410#define MPL3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
411#define MPL3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
412
413
414/*
415** F_SETUP - Bit field value definitions
416*/
417#define MPL3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */
418#define MPL3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when overflowed */
419 /* (circular buffer). */
420#define MPL3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
421/*------------------------------*/
422
423
424
425/*--------------------------------
426** Register: TIME_DLY
427** Enum: MPL3115_TIME_DLY
428** --
429** Offset : 0x10 - Time since FIFO overflow.
430** ------------------------------*/
431typedef uint8_t MPL3115_TIME_DLY_t;
432
433
434
435/*--------------------------------
436** Register: SYSMOD
437** Enum: MPL3115_SYSMOD
438** --
439** Offset : 0x11 - Current system mode.
440** ------------------------------*/
441typedef union {
442 struct {
443 uint8_t sysmod : 1; /* - System mode data bit 0. (Bits 7-1 are reserved, will always read 0.) */
444
445 } b;
446 uint8_t w;
447} MPL3115_SYSMOD_t;
448
449
450/*
451** SYSMOD - Bit field mask definitions
452*/
453#define MPL3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01)
454#define MPL3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
455
456
457/*
458** SYSMOD - Bit field value definitions
459*/
460#define MPL3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
461#define MPL3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */
462/*------------------------------*/
463
464
465
466/*--------------------------------
467** Register: INT_SOURCE
468** Enum: MPL3115_INT_SOURCE
469** --
470** Offset : 0x12 - Interrupt status. The bits that are set (logic �1�) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic �0�) indicate which function has not asserted its interrupt.
471** ------------------------------*/
472typedef union {
473 struct {
474 uint8_t src_tchg : 1; /* Delta T interrupt status bit. */
475
476 uint8_t src_pchg : 1; /* Delta P interrupt status bit. */
477
478 uint8_t src_tth : 1; /* Temperature threshold interrupt. */
479
480 uint8_t src_pth : 1; /* Altitude/Pressure threshold interrupt. */
481
482 uint8_t src_tw : 1; /* Temperature alerter status bit near or equal to target temperature. */
483
484 uint8_t src_pw : 1; /* Altitude/Pressure alerter status bit near or equal to target */
485 /* Pressure/Altitude. */
486
487 uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
488
489 uint8_t src_drdy : 1; /* Data ready interrupt status bit. */
490
491 } b;
492 uint8_t w;
493} MPL3115_INT_SOURCE_t;
494
495
496/*
497** INT_SOURCE - Bit field mask definitions
498*/
499#define MPL3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01)
500#define MPL3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0)
501
502#define MPL3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02)
503#define MPL3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1)
504
505#define MPL3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04)
506#define MPL3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2)
507
508#define MPL3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08)
509#define MPL3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3)
510
511#define MPL3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10)
512#define MPL3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4)
513
514#define MPL3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20)
515#define MPL3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5)
516
517#define MPL3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
518#define MPL3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
519
520#define MPL3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80)
521#define MPL3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7)
522
523
524/*------------------------------*/
525
526
527
528/*--------------------------------
529** Register: PT_DATA_CFG
530** Enum: MPL3115_PT_DATA_CFG
531** --
532** Offset : 0x13 - Data event flag configuration.
533** ------------------------------*/
534typedef union {
535 struct {
536 uint8_t tdefe : 1; /* Data event flag enable on new Temperature data. */
537
538 uint8_t pdefe : 1; /* Data event flag enable on new Pressure/Altitude data. */
539
540 uint8_t drem : 1; /* Data ready event mode. */
541
542 } b;
543 uint8_t w;
544} MPL3115_PT_DATA_CFG_t;
545
546
547/*
548** PT_DATA_CFG - Bit field mask definitions
549*/
550#define MPL3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01)
551#define MPL3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0)
552
553#define MPL3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02)
554#define MPL3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1)
555
556#define MPL3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04)
557#define MPL3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2)
558
559
560/*
561** PT_DATA_CFG - Bit field value definitions
562*/
563#define MPL3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
564#define MPL3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */
565 /* Temperature data. */
566#define MPL3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
567#define MPL3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */
568 /* Pressure/Altitude data. */
569#define MPL3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
570#define MPL3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */
571 /* event flag on new Pressure/Altitude or */
572 /* Temperature data. */
573/*------------------------------*/
574
575
576
577/*--------------------------------
578** Register: BAR_IN_MSB
579** Enum: MPL3115_BAR_IN_MSB
580** --
581** Offset : 0x14 - Bits 8-15 of Barometric input for Altitude calculation.
582** ------------------------------*/
583typedef uint8_t MPL3115_BAR_IN_MSB_t;
584
585
586/*--------------------------------
587** Register: BAR_IN_LSB
588** Enum: MPL3115_BAR_IN_LSB
589** --
590** Offset : 0x15 - Bits 0-7 of Barometric input for Altitude calculation.
591** ------------------------------*/
592typedef uint8_t MPL3115_BAR_IN_LSB_t;
593
594
595
596/*--------------------------------
597** Register: P_TGT_MSB
598** Enum: MPL3115_P_TGT_MSB
599** --
600** Offset : 0x16 - Bits 8-15 of Pressure/Altitude target value.
601** ------------------------------*/
602typedef uint8_t MPL3115_P_TGT_MSB_t;
603
604
605/*--------------------------------
606** Register: P_TGT_LSB
607** Enum: MPL3115_P_TGT_LSB
608** --
609** Offset : 0x17 - Bits 0-7 of Pressure/Altitude target value.
610** ------------------------------*/
611typedef uint8_t MPL3115_P_TGT_LSB_t;
612
613
614
615/*--------------------------------
616** Register: T_TGT
617** Enum: MPL3115_T_TGT
618** --
619** Offset : 0x18 - Temperature target value.
620** ------------------------------*/
621typedef uint8_t MPL3115_T_TGT_t;
622
623
624
625/*--------------------------------
626** Register: P_WND_MSB
627** Enum: MPL3115_P_WND_MSB
628** --
629** Offset : 0x19 - Bits 8-15 of Pressure/Altitude window value.
630** ------------------------------*/
631typedef uint8_t MPL3115_P_WND_MSB_t;
632
633
634/*--------------------------------
635** Register: P_WND_LSB
636** Enum: MPL3115_P_WND_LSB
637** --
638** Offset : 0x1A - Bits 0-7 of Pressure/Altitude window value.
639** ------------------------------*/
640typedef uint8_t MPL3115_P_WND_LSB_t;
641
642
643
644/*--------------------------------
645** Register: T_WND
646** Enum: MPL3115_T_WND
647** --
648** Offset : 0x1B - Temperature window value.
649** ------------------------------*/
650typedef uint8_t MPL3115_T_WND_t;
651
652
653
654/*--------------------------------
655** Register: P_MIN_MSB
656** Enum: MPL3115_P_MIN_MSB
657** --
658** Offset : 0x1C - Bits 12-19 of 20-bit Minimum Pressure/Altitude data.
659** ------------------------------*/
660typedef uint8_t MPL3115_P_MIN_MSB_t;
661
662
663/*--------------------------------
664** Register: P_MIN_CSB
665** Enum: MPL3115_P_MIN_CSB
666** --
667** Offset : 0x1D - Bits 4-11 of 20-bit Minimum Pressure/Altitude data.
668** ------------------------------*/
669typedef uint8_t MPL3115_P_MIN_CSB_t;
670
671
672/*--------------------------------
673** Register: P_MIN_LSB
674** Enum: MPL3115_P_MIN_LSB
675** --
676** Offset : 0x1E - Bits 0-3 of 20-bit Minimum Pressure/Altitude data.
677** ------------------------------*/
678typedef union {
679 struct {
680 uint8_t _reserved_ : 4;
681 uint8_t minpad : 4; /* - 20-bit Minimum Pressure/Altitude data bits 3:0. */
682
683 } b;
684 uint8_t w;
685} MPL3115_P_MIN_LSB_t;
686
687
688/*
689** P_MIN_LSB - Bit field mask definitions
690*/
691#define MPL3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0)
692#define MPL3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4)
693
694
695/*------------------------------*/
696
697
698
699/*--------------------------------
700** Register: T_MIN_MSB
701** Enum: MPL3115_T_MIN_MSB
702** --
703** Offset : 0x1F - Bits 4-11 of 12-bit Minimum Temperature data.
704** ------------------------------*/
705typedef uint8_t MPL3115_T_MIN_MSB_t;
706
707
708/*--------------------------------
709** Register: T_MIN_LSB
710** Enum: MPL3115_T_MIN_LSB
711** --
712** Offset : 0x20 - Bits 0-3 of 12-bit Minimum Temperature data.
713** ------------------------------*/
714typedef union {
715 struct {
716 uint8_t _reserved_ : 4;
717 uint8_t mintd : 4; /* - 12-bit Minimum Temperature data bits 3:0. */
718
719 } b;
720 uint8_t w;
721} MPL3115_T_MIN_LSB_t;
722
723
724/*
725** T_MIN_LSB - Bit field mask definitions
726*/
727#define MPL3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0)
728#define MPL3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4)
729
730
731/*------------------------------*/
732
733
734
735/*--------------------------------
736** Register: P_MAX_MSB
737** Enum: MPL3115_P_MAX_MSB
738** --
739** Offset : 0x21 - Bits 12-19 of 20-bit Maximum Pressure/Altitude data.
740** ------------------------------*/
741typedef uint8_t MPL3115_P_MAX_MSB_t;
742
743
744/*--------------------------------
745** Register: P_MAX_CSB
746** Enum: MPL3115_P_MAX_CSB
747** --
748** Offset : 0x22 - Bits 4-11 of 20-bit Maximum Pressure/Altitude data.
749** ------------------------------*/
750typedef uint8_t MPL3115_P_MAX_CSB_t;
751
752
753/*--------------------------------
754** Register: P_MAX_LSB
755** Enum: MPL3115_P_MAX_LSB
756** --
757** Offset : 0x23 - Bits 0-3 of 20-bit Maximum Pressure/Altitude data.
758** ------------------------------*/
759typedef union {
760 struct {
761 uint8_t _reserved_ : 4;
762 uint8_t maxpad : 4; /* - 20-bit Maximum Pressure/Altitude data bits 3:0. */
763
764 } b;
765 uint8_t w;
766} MPL3115_P_MAX_LSB_t;
767
768
769/*
770** P_MAX_LSB - Bit field mask definitions
771*/
772#define MPL3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0)
773#define MPL3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4)
774
775
776/*------------------------------*/
777
778
779
780/*--------------------------------
781** Register: T_MAX_MSB
782** Enum: MPL3115_T_MAX_MSB
783** --
784** Offset : 0x24 - Bits 4-11 of 12-bit Maximum Temperature data.
785** ------------------------------*/
786typedef uint8_t MPL3115_T_MAX_MSB_t;
787
788
789/*--------------------------------
790** Register: T_MAX_LSB
791** Enum: MPL3115_T_MAX_LSB
792** --
793** Offset : 0x25 - Bits 0-3 of 12-bit Maximum Temperature data.
794** ------------------------------*/
795typedef union {
796 struct {
797 uint8_t _reserved_ : 4;
798 uint8_t maxtd : 4; /* - 12-bit Maximum Temperature data bits 3:0. */
799
800 } b;
801 uint8_t w;
802} MPL3115_T_MAX_LSB_t;
803
804
805/*
806** T_MAX_LSB - Bit field mask definitions
807*/
808#define MPL3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0)
809#define MPL3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4)
810
811
812/*------------------------------*/
813
814
815
816/*--------------------------------
817** Register: CTRL_REG1
818** Enum: MPL3115_CTRL_REG1
819** --
820** Offset : 0x26 - Control Register 1: Modes, Oversampling.
821** ------------------------------*/
822typedef union {
823 struct {
824 uint8_t sbyb : 1; /* Operation Mode. */
825
826 uint8_t ost : 1; /* OST bit to initiate a measurement immediately, If the SBYB bit is set to */
827 /* active. */
828
829 uint8_t rst : 1; /* Software Reset. This bit is used to activate the software reset. */
830
831 uint8_t os : 3; /* Oversample Ratio. These bits select the oversampling ratio. */
832
833 uint8_t raw : 1; /* RAW output mode. RAW bit will output ADC data with no post processing, */
834 /* except for oversampling. */
835
836 uint8_t alt : 1; /* Altimeter-Barometer mode. */
837
838 } b;
839 uint8_t w;
840} MPL3115_CTRL_REG1_t;
841
842
843/*
844** CTRL_REG1 - Bit field mask definitions
845*/
846#define MPL3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01)
847#define MPL3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0)
848
849#define MPL3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02)
850#define MPL3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1)
851
852#define MPL3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04)
853#define MPL3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2)
854
855#define MPL3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38)
856#define MPL3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3)
857
858#define MPL3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40)
859#define MPL3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6)
860
861#define MPL3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80)
862#define MPL3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7)
863
864
865/*
866** CTRL_REG1 - Bit field value definitions
867*/
868#define MPL3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */
869#define MPL3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */
870#define MPL3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */
871#define MPL3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */
872#define MPL3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */
873#define MPL3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */
874#define MPL3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */
875#define MPL3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 ms */
876#define MPL3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 ms */
877#define MPL3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 ms */
878#define MPL3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */
879 /* ms */
880#define MPL3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */
881 /* ms */
882#define MPL3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */
883 /* ms */
884#define MPL3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples 512 */
885 /* ms */
886#define MPL3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */
887#define MPL3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */
888#define MPL3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */
889#define MPL3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */
890/*------------------------------*/
891
892
893
894/*--------------------------------
895** Register: CTRL_REG2
896** Enum: MPL3115_CTRL_REG2
897** --
898** Offset : 0x27 - Control Register 2: Acquisition time step.
899** ------------------------------*/
900typedef union {
901 struct {
902 uint8_t st : 4; /* Auto acquisition time step.. */
903
904 uint8_t alarm_sel : 1; /* The bit selects the Target value for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
905
906 uint8_t load_output : 1; /* This is to load the target values for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
907
908 } b;
909 uint8_t w;
910} MPL3115_CTRL_REG2_t;
911
912
913/*
914** CTRL_REG2 - Bit field mask definitions
915*/
916#define MPL3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F)
917#define MPL3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0)
918
919#define MPL3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10)
920#define MPL3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4)
921
922#define MPL3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20)
923#define MPL3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5)
924
925
926/*
927** CTRL_REG2 - Bit field value definitions
928*/
929#define MPL3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */
930 /* used. */
931#define MPL3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */
932 /* the interrupts SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
933#define MPL3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */
934#define MPL3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */
935 /* target values for the interrupts. */
936/*------------------------------*/
937
938
939
940/*--------------------------------
941** Register: CTRL_REG3
942** Enum: MPL3115_CTRL_REG3
943** --
944** Offset : 0x28 - Control Register 3: Interrupt pin configuration.
945** ------------------------------*/
946typedef union {
947 struct {
948 uint8_t pp_od2 : 1; /* This bit configures the interrupt pad INT2 to Push-Pull or in Open Drain */
949 /* mode. */
950
951 uint8_t ipol2 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT2. */
952
953 uint8_t _reserved_ : 2;
954 uint8_t pp_od1 : 1; /* This bit configures the interrupt pad INT1 to Push-Pull or in Open Drain */
955 /* mode. */
956
957 uint8_t ipol1 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT1. */
958
959 } b;
960 uint8_t w;
961} MPL3115_CTRL_REG3_t;
962
963
964/*
965** CTRL_REG3 - Bit field mask definitions
966*/
967#define MPL3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01)
968#define MPL3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0)
969
970#define MPL3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02)
971#define MPL3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1)
972
973#define MPL3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10)
974#define MPL3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4)
975
976#define MPL3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20)
977#define MPL3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5)
978
979
980/*
981** CTRL_REG3 - Bit field value definitions
982*/
983#define MPL3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
984#define MPL3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */
985#define MPL3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */
986#define MPL3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */
987#define MPL3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
988#define MPL3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */
989#define MPL3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */
990#define MPL3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */
991/*------------------------------*/
992
993
994
995/*--------------------------------
996** Register: CTRL_REG4
997** Enum: MPL3115_CTRL_REG4
998** --
999** Offset : 0x29 - Control Register 4: Interrupt enables.
1000** ------------------------------*/
1001typedef union {
1002 struct {
1003 uint8_t int_en_tchg : 1; /* Temperature Change Interrupt Enable. */
1004
1005 uint8_t int_en_pchg : 1; /* Pressure Change Interrupt Enable. */
1006
1007 uint8_t int_en_tth : 1; /* Temperature Threshold Interrupt Enable. */
1008
1009 uint8_t int_en_pth : 1; /* Pressure Threshold Interrupt Enable. */
1010
1011 uint8_t int_en_tw : 1; /* Temperature window Interrupt Enable. */
1012
1013 uint8_t int_en_pw : 1; /* Pressure window Interrupt Enable. */
1014
1015 uint8_t int_en_fifo : 1; /* FIFO Interrupt Enable. */
1016
1017 uint8_t int_en_drdy : 1; /* Data Ready Interrupt Enable. */
1018
1019 } b;
1020 uint8_t w;
1021} MPL3115_CTRL_REG4_t;
1022
1023
1024/*
1025** CTRL_REG4 - Bit field mask definitions
1026*/
1027#define MPL3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01)
1028#define MPL3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0)
1029
1030#define MPL3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02)
1031#define MPL3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1)
1032
1033#define MPL3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04)
1034#define MPL3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2)
1035
1036#define MPL3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08)
1037#define MPL3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3)
1038
1039#define MPL3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10)
1040#define MPL3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4)
1041
1042#define MPL3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20)
1043#define MPL3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5)
1044
1045#define MPL3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1046#define MPL3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1047
1048#define MPL3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80)
1049#define MPL3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7)
1050
1051
1052/*
1053** CTRL_REG4 - Bit field value definitions
1054*/
1055#define MPL3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */
1056#define MPL3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */
1057#define MPL3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */
1058#define MPL3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */
1059#define MPL3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */
1060#define MPL3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */
1061#define MPL3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */
1062#define MPL3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */
1063#define MPL3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */
1064#define MPL3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */
1065#define MPL3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */
1066#define MPL3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */
1067#define MPL3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1068#define MPL3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */
1069#define MPL3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1070#define MPL3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */
1071/*------------------------------*/
1072
1073
1074
1075/*--------------------------------
1076** Register: CTRL_REG5
1077** Enum: MPL3115_CTRL_REG5
1078** --
1079** Offset : 0x2A - Control Register 5: Interrupt output pin assignment.
1080** ------------------------------*/
1081typedef union {
1082 struct {
1083 uint8_t int_cfg_tchg : 1; /* Temperature Change INT1/INT2 Configuration. */
1084
1085 uint8_t int_cfg_pchg : 1; /* Pressure Change INT1/INT2 Configuration. */
1086
1087 uint8_t int_cfg_tth : 1; /* Temperature Threshold INT1/INT2 Configuration. */
1088
1089 uint8_t int_cfg_pth : 1; /* Pressure Threshold INT1/INT2 Configuration. */
1090
1091 uint8_t int_cfg_tw : 1; /* Temperature window INT1/INT2 Configuration. */
1092
1093 uint8_t int_cfg_pw : 1; /* Pressure window INT1/INT2 Configuration. */
1094
1095 uint8_t int_cfg_fifo : 1; /* FIFO INT1/INT2 Configuration. */
1096
1097 uint8_t int_cfg_drdy : 1; /* Data Ready INT1/INT2 Configuration. */
1098
1099 } b;
1100 uint8_t w;
1101} MPL3115_CTRL_REG5_t;
1102
1103
1104/*
1105** CTRL_REG5 - Bit field mask definitions
1106*/
1107#define MPL3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01)
1108#define MPL3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0)
1109
1110#define MPL3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02)
1111#define MPL3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1)
1112
1113#define MPL3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04)
1114#define MPL3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2)
1115
1116#define MPL3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08)
1117#define MPL3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3)
1118
1119#define MPL3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10)
1120#define MPL3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4)
1121
1122#define MPL3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20)
1123#define MPL3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5)
1124
1125#define MPL3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1126#define MPL3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1127
1128#define MPL3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80)
1129#define MPL3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7)
1130
1131
1132/*
1133** CTRL_REG5 - Bit field value definitions
1134*/
1135#define MPL3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1136#define MPL3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */
1137#define MPL3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1138#define MPL3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */
1139#define MPL3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1140#define MPL3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */
1141#define MPL3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1142#define MPL3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */
1143#define MPL3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1144#define MPL3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */
1145#define MPL3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1146#define MPL3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */
1147#define MPL3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1148#define MPL3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */
1149#define MPL3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1150#define MPL3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */
1151/*------------------------------*/
1152
1153
1154
1155/*--------------------------------
1156** Register: OFF_P
1157** Enum: MPL3115_OFF_P
1158** --
1159** Offset : 0x2B - Pressure data offset.
1160** ------------------------------*/
1161typedef uint8_t MPL3115_OFF_P_t;
1162
1163
1164
1165/*--------------------------------
1166** Register: OFF_T
1167** Enum: MPL3115_OFF_T
1168** --
1169** Offset : 0x2C - Temperature data offset.
1170** ------------------------------*/
1171typedef uint8_t MPL3115_OFF_T_t;
1172
1173
1174
1175/*--------------------------------
1176** Register: OFF_H
1177** Enum: MPL3115_OFF_H
1178** --
1179** Offset : 0x2D - Altitude data offset.
1180** ------------------------------*/
1181typedef uint8_t MPL3115_OFF_H_t;
1182
1183
1184#endif /* MPL3115_H_ */
MPL3115_CTRL_REG1_t
Definition mpl3115.h:822
MPL3115_CTRL_REG2_t
Definition mpl3115.h:900
MPL3115_CTRL_REG3_t
Definition mpl3115.h:946
MPL3115_CTRL_REG4_t
Definition mpl3115.h:1001
MPL3115_CTRL_REG5_t
Definition mpl3115.h:1081
MPL3115_DR_STATUS_t
Definition mpl3115.h:165
MPL3115_F_SETUP_t
Definition mpl3115.h:393
MPL3115_F_STATUS_t
Definition mpl3115.h:339
MPL3115_INT_SOURCE_t
Definition mpl3115.h:472
MPL3115_OUT_P_DELTA_LSB_t
Definition mpl3115.h:266
MPL3115_OUT_P_LSB_t
Definition mpl3115.h:102
MPL3115_OUT_T_DELTA_LSB_t
Definition mpl3115.h:302
MPL3115_OUT_T_LSB_t
Definition mpl3115.h:138
MPL3115_P_MAX_LSB_t
Definition mpl3115.h:759
MPL3115_P_MIN_LSB_t
Definition mpl3115.h:678
MPL3115_PT_DATA_CFG_t
Definition mpl3115.h:534
MPL3115_SYSMOD_t
Definition mpl3115.h:441
MPL3115_T_MAX_LSB_t
Definition mpl3115.h:795
MPL3115_T_MIN_LSB_t
Definition mpl3115.h:714
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